Side-Channel Attack

What Is a Side-Channel Attack?

A side-channel attack is a method of extracting secret information from a cryptographic system by observing its physical behavior during computation rather than attacking the underlying algorithm. Instead of trying to break the math behind elliptic curve cryptography or SHA-256, an attacker measures unintended signals: how long an operation takes, how much power the chip draws, or what electromagnetic radiation it emits.

The concept dates to at least 1943, when a Bell Telephone engineer observed decipherable spikes on an oscilloscope correlated with an encrypting teletype's output. The field was formalized by Paul Kocher's 1996 paper at CRYPTO, which demonstrated that measuring execution time variations could recover private keys from RSA, Diffie-Hellman, and DSS implementations. His experiments recovered 90% of bits in 512-bit RSA keys after observing roughly 20,000 operations.

Side-channel attacks matter for Bitcoin because every transaction involves digital signatures computed with private keys. If an attacker can observe the signing process closely enough, they can recover the key and steal funds, even if the cryptographic algorithm itself is mathematically sound.

How It Works

All side-channel attacks follow the same general principle: a cryptographic operation that processes secret data produces observable physical effects that correlate with that data. The attacker measures those effects, applies statistical analysis, and reconstructs the secret. The main categories differ in which physical signal they exploit.

Timing Attacks

Timing attacks measure how long a cryptographic operation takes to complete. If the code contains conditional branches that depend on secret key bits (for example, skipping a multiplication when a key bit is zero), the total execution time reveals information about the key. Even nanosecond-scale differences become exploitable with enough measurements.

Brumley and Boneh demonstrated in 2003 that timing attacks work remotely over a network, not just with physical access. For Bitcoin, this means any signing implementation with data-dependent branches could leak private key bits to an observer measuring response times.

Power Analysis

Power analysis attacks monitor the electrical power consumed by a chip during cryptographic computation. Two forms exist:

• Simple Power Analysis (SPA): interprets a single power trace from one execution. In elliptic curve scalar multiplication, point doubling and point addition operations consume visibly different amounts of power. A single trace can reveal the sequence of doubles and adds, directly exposing the scalar (private key) bits.
• Differential Power Analysis (DPA): uses statistical analysis across thousands of power traces to correlate consumption with intermediate computed values. Introduced by Paul Kocher, Joshua Jaffe, and Benjamin Jun in 1999, DPA can extract keys even from implementations with some SPA protections. As few as 1,000 encryptions proved sufficient to recover a secret key from a smart card.

Electromagnetic Analysis

Electromagnetic (EM) analysis captures radiation emitted by a processor during computation. Researchers have demonstrated ECDSA key extraction from mobile devices using a simple magnetic probe placed near the device, operating at only a few hundred kHz bandwidth. Genkin, Shamir, and Tromer extracted full signing keys from OpenSSL and CoreBitcoin on iOS using an improvised probe and a standard audio card.

Cache-Timing Attacks

Cache-timing attacks exploit the speed difference between CPU cache hits and cache misses. Two primary techniques:

• Flush+Reload: the attacker flushes a shared cache line, waits for the victim to compute, then measures reload time to determine if the victim accessed that memory. This technique has extracted 256-bit AES keys from OpenSSL in as few as 10,000 samples (roughly 135 milliseconds).
• Prime+Probe: the attacker fills a cache set with their own data, then checks whether the victim displaced any entries. Unlike Flush+Reload, this does not require shared memory between attacker and victim.

Cache-timing attacks are especially relevant for cloud-hosted Bitcoin infrastructure where multiple tenants share physical CPU hardware.

Acoustic and Frequency-Based Attacks

More exotic side channels include acoustic cryptanalysis (recording sounds emitted by electronic components during decryption) and frequency-scaling attacks. Genkin, Shamir, and Tromer demonstrated extraction of 4096-bit RSA keys from a laptop within an hour by recording high-pitched sounds with a mobile phone placed nearby.

The Hertzbleed attack, disclosed in 2022, exploits dynamic voltage and frequency scaling (DVFS) in modern processors. CPU clock frequency varies with the data being processed, turning constant-time code into variable-time code. This affects all Intel processors and many AMD and ARM chips, and no microcode patches are planned.

Bitcoin-Specific Defenses

The Bitcoin ecosystem has developed multiple layers of defense against side-channel attacks, from carefully written cryptographic libraries to specialized hardware.

Constant-Time Code in libsecp256k1

Bitcoin Core's libsecp256k1 library implements comprehensive side-channel resistance:

• Constant-time, constant-memory-access signing and public key generation: the sequence of instructions, branches, and memory addresses accessed is identical regardless of secret values.
• Branch-free conditional moves: table lookups use conditional moves instead of branches, preventing cache-timing attacks from distinguishing which table entry was selected.
• Optional runtime blinding: random blinding values are added before scalar multiplication and removed afterward, frustrating differential power analysis even if the attacker controls inputs.
• RFC 6979 deterministic nonces: eliminates catastrophic private key leakage from nonce reuse or poor random number generation by deriving the nonce deterministically from the private key and message via HMAC-DRBG.

These protections require ongoing vigilance. Certain compiler versions (GCC 13+, Clang 14+) have been found to introduce non-constant-time behavior through optimization, breaking guarantees that hold at the source code level.

Hardware Wallet Protections

Signing devices and hardware wallets use secure elements to resist physical side-channel attacks. These certified chips (Common Criteria EAL5+ or EAL6+) include hardware-level countermeasures:

• Power consumption noise injection that masks the correlation between computation and energy draw
• Voltage and clock glitch detection that halts operation if tampering is detected
• Metal mesh tamper detection layers that resist physical probing
• Hardened logic cells designed to resist DPA and SPA

Hardware wallets without secure elements remain vulnerable. In 2019, the Ledger Donjon team demonstrated PIN recovery from a Trezor One using power analysis: they measured power consumption at 3 GS/s during PIN verification, built machine-learning classifiers from 200,000 profiling traces, and achieved 100% PIN recovery after only 10 power traces. For a deeper analysis of these attack vectors, see the hardware wallet attack vectors research article.

FROST Threshold Signing

FROST threshold signatures provide a structural defense against side-channel attacks. Because each participant holds only a key share rather than the full signing key, compromising a single signer via side-channel analysis yields only a share. An attacker would need to side-channel enough participants to meet the threshold (for example, 3 of 5 signers) to reconstruct the full key.

RFC 9591, the official IETF specification for FROST, explicitly addresses side-channel resistance. It requires that scalar multiplication, base-point multiplication, and serialization routines be implemented in constant time. Spark's use of FROST for signing operations means that side-channel resistance is distributed across multiple participants rather than concentrated in a single device. For a deeper look, see the FROST threshold signatures research article.

Notable Examples

Minerva Attack (2019)

Discovered by researchers at Masaryk University, the Minerva attack exploits ECDSA nonce bit-length leakage through timing differences in scalar multiplication. Each additional bit in the nonce adds one loop iteration, creating a measurable timing variation. By collecting roughly 2,100 signatures and solving a lattice reduction problem, researchers recovered 256-bit private keys from smart cards and software libraries including libgcrypt, wolfSSL, and OpenJDK's SunEC provider.

Spectre and Meltdown (2018)

These processor-level vulnerabilities exploited speculative execution to read protected memory, affecting virtually all modern Intel, AMD, and ARM processors. For cryptocurrency infrastructure, the implications were significant: cloud-hosted exchange hot wallets and mining operations running on shared hardware were vulnerable. Multiple exchanges restricted wallet functions during emergency patching. Hardware wallets were unaffected because they do not run general-purpose operating systems.

Hertzbleed (2022)

By exploiting dynamic frequency scaling, Hertzbleed demonstrated that even correctly implemented constant-time code can leak secrets through remote timing analysis. The attack showed that current constant-time programming guidelines are insufficient to guarantee constant-time execution on modern processors, because the CPU itself introduces data-dependent timing variations.

Mitigations

Defending against side-channel attacks requires a layered approach spanning software, hardware, and operational practices.

Software Defenses

• Constant-time algorithms: eliminate all branches, memory access patterns, and timing variations that depend on secret data. This is the foundation of side-channel resistance in libraries like libsecp256k1.
• Blinding and masking: introduce randomness into intermediate values so that power consumption and EM emissions do not correlate with actual secrets.
• Hedged signatures: mix fresh randomness into deterministic nonce derivation (as proposed in the IETF draft on hedged signatures) to resist fault injection attacks that exploit the repeatability of RFC 6979.
• Compiler verification: regularly audit compiled output to ensure optimization passes do not reintroduce data-dependent branches.

Hardware Defenses

• Secure elements with Common Criteria certification (EAL5+) provide physical-layer protections against power analysis and fault injection.
• Hardware security modules (HSMs) protect institutional signing keys with tamper-evident enclosures and dedicated cryptographic processors.
• Air-gapped signing eliminates remote timing attack vectors entirely by keeping keys on devices with no network connectivity.

Architectural Defenses

• Threshold signatures (like FROST) distribute key material across multiple participants, requiring an attacker to compromise multiple devices rather than a single one.
• Dedicated hardware for cryptographic operations prevents cache-timing attacks that exploit shared processor resources in cloud environments.
• Regular key rotation limits the window during which a partially leaked key remains useful.

Risks and Considerations

Evolving Attack Surface

Side-channel attacks continue to advance. AI-enhanced power analysis and deep learning techniques are making attacks more automated and accurate. The 2025 discovery of sleep-based power side channels demonstrated novel ways to leak ECDSA nonces. As attack tools become more accessible, the bar for exploitation drops.

Physical Access Requirements

Most power analysis and EM attacks require physical proximity to the target device, which limits their practical applicability. However, cache-timing and remote timing attacks work over networks, and Hertzbleed-class attacks can potentially extract keys from any machine with data-dependent frequency scaling. The threat model depends heavily on where keys are stored and how signing is performed.

Defense in Depth

No single countermeasure is sufficient. Constant-time code can be broken by compiler optimizations or CPU frequency scaling. Secure elements can be defeated by laser fault injection (as demonstrated against the TROPIC01 chip used in the Trezor Safe 7 in January 2026). Threshold signatures raise the bar but do not eliminate risk if multiple participants are co-located. Effective defense requires combining software, hardware, and operational protections. For related threats to long-term key security, see the post-quantum cryptography research article.

This glossary entry is for informational purposes only and does not constitute financial or investment advice. Always do your own research before using any protocol or technology.